In a method for fabricating a semiconductor device, the Bosch process is sometimes used to form a through via hole. When the Bosch process is used, there is a trade-off between the processing rate (e.g., throughput) and a scallop size (i.e., the non-flatness of the side wall of a through via hole). An increase in the processing rate decreases the flatness of the side wall of the through via hole.
A decrease in the flatness of the side wall of a through via hole sometimes makes it difficult to form an insulating film, or a plating seed layer, on the side wall of the through via hole. Additional processing to improve the flatness of the side wall to reduce the amplitude of the scallops may be performed, but this increases the number of processes required to make the through silicon via hole and results in decreased throughput.